On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.
Failure Mechanisms
[As of April, 2011]
System LSI Field Failure Mode
Test Coverage
There are various System on Chip (SoC) failure models. A typical failure model is "stuck-at" failure in which the device is logically fixed to 0 or 1, regardless of the circuit input status. In general, failure simulation is used to check the effectiveness of a test pattern at the time of circuit failure detection. For example, let us presume that a faulty node becomes stuck at 0. When a pattern that changes this node to 1 is entered and the output value is compared with that of the normal circuit, the fault is detectable if the values do not match and not detectable if the values match. In this manner, failure simulation is used to check the integrity of a test program by presuming the failure of a certain node in a circuit and repeating the test program for all possible failure locations to see if the failure is detectable by the test pattern. The term "test coverage" refers to the ratio of detectable failures to the number of presumed failures in a circuit.
For a stuck-at failure, it is difficult to achieve a high failure detection rate using conventional function tests alone due to ever increasing SoC scaling. For this reason, the scan method and automatic test pattern generation (ATPG) technology are combined to achieve a high failure detection rate. Furthermore, with higher SoC speeds as a result of process miniaturization in recent years, response to stuck-at failures as well as delay failures will be increasingly in demand. A delay failure is a failure in which the circuit delay does not conform to specifications for some reason or other. Similar to stuck-at failures, it is difficult to achieve a high delay failure detection rate using conventional function tests alone. The scan method must therefore be combined with transition delay tests or other techniques to achieve a high failure detection rate. Figure 1 provides an overview of the transition test.
Figure 1 Overview of Transition Delay Test
As shown in Figure 1, the frequency test is conducted with the clock operated at the desired test frequency. The pattern is automatically generated and impressed on SoC based on an ATPG algorithm, enabling delay failure detection.
Zero Time Failure Reduction Method
The term "zero time failure" refers to a defect that occurs after shipment from Toshiba, between customer incoming inspection and product shipment. Zero time failures are estimated based on test coverage and production yield. In general, the relational expression of test coverage and defect level (DL) is as follows:
DL = 1 – Y (1 – T)
DL: Defect level, Y: Yield, T: Test pattern failure detection rate
Toshiba indicates zero time failures based on the above-described logical equation and actual field data using the formula below, utilizing the result as an index for measures for yield improvement and reduction of defects caused by test pattern inadequacies.
FDL = α {1 - Y (1 - T)} + β
FDL: Failure defect level, α, β: Coefficients, Y: Yield, T: Test coverage
On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.