On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Failure Mechanisms

[As of April, 2011]

Electrostatic Breakdown

ElectroStatic Discharge (ESD)

With advances in semiconductor device fine-pattern processing and circuit integration technologies, performance has dramatically improved. However, along with fine-pattern processing, device degradation and damage from ESD has become a major problem.
This section describes how static electricity occurs and how it damages devices.

ESD Model
1. Human Body Model (HBM)
  In this model, the human body serves as the source of static electricity, and the electrostatic discharge from the body damages devices. Although there are various discussions concerning how much static charge the body contains, evaluations are conducted using a capacitor discharge method with values set at 100 pF, 1500 Ω.
2. Machine Model (MM)
  In this model, objects with a high static charge capacity, such as device-handling equipment made of metal, serve as the source of static electricity, and a discharge of electricity under low-resistance conditions damages devices. Evaluations are conducted using a capacity discharge method with values set at 200 pF, 0 Ω.
3. Charged Device Model (CDM)
  In this model, the device itself becomes the source of static electricity due to sticking or the friction produced when the device approaches a charged object, resulting in a sudden discharge of electricity through the leads which damages devices.
  Evaluations are conducted using dedicated CDM test equipment.
4. Other
  In addition to the above three models, there is the field-induced model (FIM) in which induced charge occurs when a device with an insulated structure, such as a MOS device, is exposed to a high electrical field, resulting in discharge that damages the device. There is also a small-size capacitor method (10 pF, 0 Ω) that reproduces CDM using the capacitor discharge method.
Breakdown Modes
1. Oxide Film Breakdown
  The dielectric breakdown strength of oxide film is generally said to be 8 to 10 MV/cm. For this reason, devices with a thin oxide film, e.g. 50 nm, exhibit dielectric breakdown at 40 to 50 V. Since MOS devices can be damaged at low voltages, it is desirable to handle the devices in ESD-protected environments.
  Oxide film breakdown in a MOS structure occurs when voltage above the threshold is applied to oxide film with low thermal conductivity, or when the energy required to inflict damage is consumed by the MOS device.
2. Junction Breakdown
  Junction breakdown occurs when excessive current flow in the junction area raises the junction temperature locally, destroying it with heat. The Wunsch & Bell model that is based on a thermal diffusion formula is the model most commonly used to explain junction breakdown. ^{Note 1} In the model, the junction breakdown phenomenon is determined from the impressed pulse width and power density applied to the device.
  Since junction energy consumption differs for a forward or reverse discharge, different breakdown voltages result. Since electrical discharge in the forward direction does not readily concentrate energy in a localized area in comparison to reverse discharge, the breakdown voltage for a forward discharge is higher.
3. Metallization Breakdown
  Metallization breakdown, similar to junction breakdown, is caused by thermal destruction. It is thought to occur when the power density (amount of heat) applied is sufficient enough to fuse metal.

Latch-up

CMOS-ICs are sometimes destroyed when an excessive noise or voltage is applied to them through the input/output pins while it is active, causing a parasitic thyristor to conduct. Figure 1 shows a CMOS sectional structure and equivalent circuit. As shown in Figure 1 CMOS Sectional Structure, CMOS has NPN and PNP parasitic transistors which form the PNPN thyristor structure shown in Figure 1 Equivalent Circuit. For example, if a voltage greater than V_DD max is applied to pin D, the emitter-to-base of Tr1 becomes forward-biased. The collector current of Tr1 drops to GND through R_P causing a potential difference to develop across R_P. This in turn forward-biases the emitter-to-base of Tr2 so that the collector current of Tr2 is supplied from V_DD through R_N, causing a potential difference to develop across R_N. Consequently, increasingly greater amounts of positive feedback are applied, forward-biasing the base-to-emitter in Tr1 and forcing the thyristor structure to conduct. In the end, the CMOS IC breaks down.

This is [Figure 1 CMOS Sectional Structure and Equivalent Circuit].

Figure 1 CMOS Sectional Structure and Equivalent Circuit

Note 1: Bibliography. D. C. Wunsch and R. R. Bell; "Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors due to Pulse Voltages," IEEE NS-15, No. 6, (1969), pp. 244-259