On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Failure Mechanisms

[As of April, 2011]

Gate Oxide Film

Oxide Film Breakdown

Since the gate oxide film of a MOS device is several nm to 100 nm thin, applying a voltage higher than the voltage resistance level results in breakdown. For example, sudden static electricity or surges readily cause breakdown. In actual operating conditions as well, the oxide film can break down over time. This is referred to as time dependent dielectric breakdown or TDDB. ^{Note 1}
Oxide film breakdown depends largely on the distribution of oxide breakdown voltage, which is based on gate oxide film defects, and the intrinsic defect density. The parameters that determine the oxide breakdown voltage distribution and intrinsic defect density are extremely complex. The values are affected by factors such as gate electrode material, film thickness, substrate defects, oxidation method and contamination.
In the case of TDDB, degradation is greatly accelerated by an increase in the electric field. Although a number of acceleration models have been proposed, a generally accepted model has not been established. In general, it is maintained that the life resulting from an increase in the electric field is proportional to the following two models:
TTF=Aexp(-βE)････E-model
TTF=Aexp(γ/E)････1/E-model
(TTF: Time to failure, β,γ: Acceleration factor, A: Coefficient, E: Electrical field)
Toshiba predicts with high accuracy the oxide film life after confirming the conformity by the voltage acceleration model. Figure 1shows an example of a life test.

This is [Figure 1 Example of TDDB Voltage Acceleration Life Test Result].

Figure 1 Example of TDDB Voltage Acceleration Life Test Result

Stress Induced Leakage

The leakage conduction mechanisms of oxide film can be broadly divided into two types: the Fowler-Nordheim tunneling current and hard breakdown (HBD) whereby insulation properties are completely lost. However, with the development of increasingly thin gate oxide films, direct tunneling current, stress induced leakage current (SILC) and soft breakdown (SBD) conduction mechanisms have been observed in thin films of 5 nm or less.

This is [Figure 2 SILC, SBD, HBD I-V Characteristics].

*SBD: Soft BreakDown, HBD: Hard BreakDown
Figure 2 SILC, SBD, HBD I-V Characteristics^{Note 2}

SILC has been observed to gradually increase leakage current from the initial stages of wear-out failure. Soft breakdown exhibits a current increase of an intermediate range, i.e., between that of hard breakdown and SILC, but results in a certain level of insulation rather than a complete short in the oxide film. This type of stress leakage is thought to affect factors such as the reliability of flash memory.

Electrical Charges in Oxide Film

Certain instability phenomena based on the electrical charges in the oxide film exist. The charges include:

Mobile ions Qm (Na⁺、H⁺)
Fixed charges Qf
Oxide-trapped charges Qot
Interface state Qit
Trapped charges generated by ionizing radiation

Figure 3 shows the charge states in the oxide film and interface.
The instability due to mobile ions 1 is considered to be caused primarily by contamination of the passivation film or by external contamination introduced into the process rather than by contamination of the gate oxide film itself.
Charges 2 and 3 do not change state due to surface potential. When these charges are generated within the oxide film, threshold voltage V_th fluctuates. Charges generated near the interface between the gate oxide film and the silicone bulk are called the fixed charges, and charges generated within the film are called the trapped charges of the oxide film.
The interfacial state 4 changes in accordance with the surface potential and is referred to as "fast state." When this state occurs in the oxide film interface, Gm is degraded.
Charges 2, 3 and 4 are being introduced in new processing and once again coming to the fore.
Furthermore, the advent in recent years of flash EEPROMs have given importance to the reliability of what is called the tunnel oxide film, a film of 10 nm or less through which electrons are injected and ejected. Program/erase cycling operations in flash EEPROM cause an increase in electron traps 3 within the oxide film, blocking the passage of electrons.
It is also known that the trap states or trapped charge generates current leakage path in low electrical fields, causing loss of stored charge when the device is not in operation or during reading. Therefore, it is critical to develop a tunnel oxide film with fewer traps to increase the number of the maximum program/erase and to improve charge-retention characteristics.

This is [Figure 3 Oxide Film and Interfacial Charges].

Figure 3 Oxide Film and Interfacial Charges^{Note 3}

Nonvolatile Memory Failure Mode^{Note 4, 5}

Nonvolatile memory (EEPROMs and flash EPROMs) store charge (electrons or holes) in electrically isolated memory cells (floating gates), thereby realizing no data loss even if the power is turned off. Electrical reprogramming operations are performed via a tunnel oxide film. The memory cells are electrically isolated by the formation of a silicon oxide film between the polycrystalline silicon floating gate and substrate silicon, and a polycrystalline oxide film – nitride film – oxide film (ONO) stacked insulating film between the polycrystalline silicon floating gate and control gate. The nonvolatile memory "1" and "0" states are determined by the amount of charge stored in the floating gate. If the insulating film that surrounding the floating gate is defect free, the stored charge will not dissipate at all. If a defect exists in the insulating film or the film degrades, leakage current will flow, causing a change in the charge amount determined by program and erase operations and, consequently, defect detection by the read operation (i.e., when voltage is applied on the control gate).

Retention failure (Improper Charge Retention)
Retention time refers to the amount of time until the charge stored in a memory cell either increases or decreases for some reason or other and retention is detected. The main cause of retention failure is leakage of charge through a defect in the film isolating the memory cell. Subsequent defects include neutral traps or positive charge traps formed in the oxide film. These defects have the same origin as SILC described.
Endurance failure (Improper Repetitive Rewrite)
Program and erase operations gradually reduce the "1" and "0" read voltage differential, resulting in window closing and operation failure. Causes include oxide charge traps and the interface state charges. With the former, a trap is formed in the tunnel oxide film, capturing electrons and causing degradation of the program speed. With the latter, program/erase cycling increases the density of the interface states, thereby decreasing the read current and causing window closing.
Disturb failure
"Disturb" refers to a change in stored charge due to voltage applied on nodes during memory cell program/erase and read operations. While in principle this type of failure is possible regardless of operation selection, a representative type is the Read-Disturb failure that occurs during read operations. A Gate-Disturb failure in particular requires caution since this type of failure introduces a charge simply when gate voltage is applied, and exhibits a maximum disturb time of 10 years. The Gate-Disturb failure prominently appears when program/erase operations are performed repeatedly. The true cause is believed to be the formation of a neutral traps or positive charge traps in the tunnel oxide film due to program/erase cycling operations, as described in Section 1 Retention failure (Improper Charge Retention), resulting in the conduction of electrons via these traps.

The following describes nonvolatile memory failure modes in further detail, using retention failure as an example.
The charge stored in a memory cell fluctuates due to the effects of the following:

Natural attenuation
Charge loss or charge injection associated with material or geometric structural defects
Charge migration associated with circuit design

Regularly observed charge loss and charge injection events include events such as the following:

a) The event occurs due to defects in the oxide film or insulating film between the polycrystalｌine silicon, often resulting in a random 1-bit failure.

b) The stored charges are lost by ionizable contamination, normally resulting in a cluster bits failure.

c) Holes generated from a drain avalanche breakdown are trapped, causing the event and resulting in a single bit failure.

d) The event occurs due to the dissipation of electrons through a defect-less section of the oxide film or insulating film between the polycrystaｌline silicon, resulting in slow leakage over an extremely long period of time.

Items a) and b) are normally checked and eliminated using the voltage acceleration and temperature acceleration methods.

Item c) is prevented by source/drain junction profile design.
Item d) results in an intrinsic retention life exceeding 100 years since the leakage is one electron or less per day.

Ionic contamination is observed under high temperature environments and is presumably caused by a positively charged alkali ion (Na⁺ or K⁺) or water or H⁺.

Program /erase cycling sometimes results in further degradation of retention characteristics and Gate-Disturb resistance. In particular, when the tunnel oxide film thickness is 8 nm or less:
e) Charge loss and charge injection failure caused by low electric field leakage due to SILC readily occur.
This leakage is believed to occur due to electron conduction via charged traps (hole trap or neutral trap). Because this is mainly determined by tunneling probability, the activation energy is low, necessitating caution during screening by the high-temperature test.

Figure 4 shows the flash memory cell structure and improper retention failure, and Figure 5 shows the band structure and leakage path in response to the representative improper retention modes a) to e).

To prevent a reduction in yield that is mainly caused by single bit failures in actual LSIs, redundancy and error correction circuits (ECCs) are introduced when mounting nonvolatile memory density becomes highers.

This is [Figure 4 Flash Memory Cell Structure and Improper Retention].

Figure 4 Flash Memory Cell Structure and Improper Retention

This is [Figure 5 Band Structure and Leakage Path].

Figure 5 Band Structure and Leakage Path

Note 1: Bibliography. D. Crook; "Method of Determining Reliability Screens for Time Dependent DielectricBreakdown," 17th Annual Proc. Re1. Phys., (1979), p. 1

Note 2: Bibliography. E. Miranda; IEEE Trans. Electric devices, Vol. 47, No.1, Jan. (2000)

Note 3: Bibliography. B. E. Deal; "Standardized Terminology for Oxide Charges Associated with Thermally Oxided Silicon," IEEE, Trans., Electron Devices, ED-27, (1980), p. 606

Note 4: Bibliography. IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays, IEEE Std 1005-1998, IEEE Electron Device Society, (1999), p. 75

Note 5: Bibliography. "Flash Memories," edited by Paolo Cappelletti, Carla Golla, Piero Olivo, and Enrico Zanoni, Kluwer Academic Publishers, (1999), p. 399