On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Failure Mechanisms

[As of April, 2011]

Semiconductor Substrates

Substrates used in semiconductor devices include Si single-crystal, Si epitaxial, GaAs and GaP substrates.
Advances in crystal processing technology have made the manufacture of dislocation-free Si single-crystal possible. Currently, attention is being paid to defects which occur during the oxidation and diffusion processes, and distortion, micro-cracks and staking faults known as OSFs (oxidation-induced stacking faults) which occur during the crystal-forming process. These types of crystal defects increase the reverse current in the PN junction when dense, degrading the retention time characteristics in DRAM and causing a slight leakage current in SRAM. In bipolar devices, these defects degrade the breakdown voltage^{Note 1} and reduce h_FE. Countermeasures include oxygen density control in the crystal, optimization of gettering and other processes, and cleaning.
If the resistance formed in the Si substrate deviates from the designed value due to a piezo-resistance effect caused by stress from resin mold distortion, problems that affect yields and reliability occur. Countermeasures include encapsulating the device in low-stress resin or incorporating the estimated amount of deviation in the design in advance.

PN Junction

With pattern designs and product process designs, characteristic failures due to PN junction degradation have virtually disappeared. However, continuing progress in microscopic process development has increased the possibility of malfunction, degradation and breakdown due to external stress factors.
One such factor is “latch-up.” This phenomenon is caused by an excessive current flow between the power supply and GND when parasitic PNP and NPN transistors turn on due to the nature of the device’s structure. This readily occurs in CMOS devices in particular. The failure mode that occurs with this phenomenon is open failure in Al metallization or bonding wire.
One possible cause of latch-up is electrical noise that exceeds the maximum rated value (i.e., electrical over stress or EOS). Countermeasures include lowering the h_FE of parasitic transistors which readily cause latch-up, and optimizing the pattern design. However, precautions must also be taken regarding operating conditions. (See Handling Precautions.)
Another example of external stress is electrostatic discharge (ESD), which is caused by static electricity. When ESD is applied in the reverse direction to the PN junction, localized heat that results from power consumption melts the Si, damaging the junction. Countermeasures generally taken include the insertion of resistors and protective diodes to improve the dispersion of the voltage and current.

Alloy Spikes

The primary metallization material for semiconductor devices is Al. Al has low electrical resistance compared to other materials, resulting in superior adherence to insulating materials such as silicon oxide film. Nevertheless, high –temperature treatment can cause the silicon in the silicon substrate to flow into the Al film and damage the junction in the area of the contact. This failure is referred to as an alloy spike. Alloy spikes cause breakdown voltage degradation and shorts, especially in shallow junctions.
Countermeasures include adding silicon to the Al, and forming a barrier metal between the Al and silicon.

Note 1: Bibliography. Nicholas E. Lycoudes; "Semiconductor Instability Failure Mechanisms Review," IEEE Trans. on Reliability, Vol. R-29, No.3, August, (1980), p. 237