Toshiba Corporation Semiconductor & Storage Products Company
HOME > Products > Reliability Information > Semiconductor Device Reliability > Failure Rate Estimation Methods

On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Estimating Electronic Equipment Failure Rates Using MIL-HDBK-217

[As of April, 2011]

MIL-HDBK-217 is a widely used databook containing estimations of the failure rate of semiconductor devices based on actual field performance data.
MIL-HDBK-217 contains two reliability prediction methods: Part Stress Analysis and Parts Count Analysis. Part Stress Analysis method requires a large amount of detailed information while Parts Count Analysis requires less information than Part Stress Analysis does, like part quantities, part quality level, and application environment.
In MIL-HDBK-217, is the data containing a large collection of field data for MIL-standard electronic equipment. As a standard for procuring military equipment, MIL-HDBK-217 is considered stringent in terms of safety, predicting failure rates one or two orders of magnitude greater than actual failure rates.
Therefore, if applied to general use, estimated failure rates for some semiconductor devices, especially ICs and LSIs, will not match actual performance rates for reasons such as the following:

  1. Semiconductor devices, especially ICs and LSIs, are undergoing rapid technological innovations. Accordingly, the MIL-HDBK-217 database figures do not necessarily reflect the current technology level, i.e., the reliability level of current devices.
  2. Although a constant failure rate (following an exponential distribution) is assumed in MIL-HDBK-217, the failure rate in the case of semiconductor devices tends to decrease as the initial defects or intrinsic defects reduce with time. Therefore, it may become necessary to correct the estimated failure rate depending on the target time for which the estimation was made.
  3. Although failure rates must be correlated with failure mechanisms in order to accurately obtain failure rate estimations, failure modes are closely interrelated with device structure and process technology. In MIL-HDBK-217, these points are simplified. As a result, actual device performance in relation to temperature, for example, will differ from that predicted by MIL-HDBK-217.

Semiconductor devices, especially ICs and LSIs, are being improved continuously, with their functionality and degree of integration advancing rapidly. The same can be said for reliability. The failure rate of individual products is improving year by year. Overall, even for new products with increased functionality and integration, the failure rate per device does not increase proportionately with the level of increase in integration, but rather remains roughly constant. In the following section, the Part Stress Analysis method is described.

IC/LSI Failure Rate Model (Part Stress Analysis Prediction)

The Part Stress Analysis method contains failure models for part and component categories. The basic failure rate formula for devices including microprocessors, MOS devices, digital/linear gate alleys and logic alleys, bipolar devices, digital/linear gate alleys and logic alleys is as follows:


This is [the equation for the basic failure rate for devices].

Where,

λp: Divice failure rate per 106 hours
C1: Circuit complexity failure rate
πT: Temperature factor,
C2: Package complexity failure rate
πE: Environment factor
πQ: Quality factor
πL: Learning factor

Failure rate models for discrete semiconductor devices, CMOS devices with more than sixty thousands gates and memory devices are separately described.
The factors in the failure rate formula are detailed below.

  1. C1: Die Complexity Failure Rate
    Table 1 Bipolar Digital and Linear Gate/Logic Array Die Complexity Failure Rate-C1
    Digital Linear PLA/PAL
    No. Gates C1 No. Transistors C1 No. Gates C1
    1 to 100 0.0025 1 to 100 0.010 Up to 200 0.010
    101 to 1,000 0.0050 101 to 1,000 0.020 201 to 1,000 0.021
    1,001 to 3,000 0.010 1,001 to 3,000 0.040 1,001 to 5,000 0.042
    3,001 to 10,000 0.020 3,001 to 10,000 0.060 - -
    10,001 to 30,000 0.040 - - - -
    30,001 to 60,000 0.080 - - - -
    Table 2 MOS Linear and Digital Gate/Logic Array Die Complexity Failure Rate-C1Note
    Digital Linear PLA/PAL
    No. Gates C1 No. Transistors C1 No. Gates C1
    1 to 100 0.010 1 to 100 0.010 Up to 500 0.00085
    101 to 1,000 0.020 101 to 300 0.020 501 to 1,000 0.0017
    1,001 to 3,000 0.040 301 to 1,000 0.040 2,001 to 5,000 0.0034
    3,001 to 10,000 0.080 1,001 to 10,000 0.060 5,001 to 20,000 0.0068
    10,001 to 30,000 0.16 - - - -
    30,001 to 60,000 0.29 - - - -

    Note: For CMOS gate counts above 60,000 use the VHSIC/VHSIC-Like model in Section 5.3 (of MIL-HDBK-217)

    Table 3 Microprocessor Die Complexity Failure Rate-C1
    No. Bits Bipolar MOS
    C1 C1
    Up to 8 0.060 0.14
    Up to 16 0.12 0.28
    Up to 32 0.24 0.56
  2. πT: Temperature Factor
    Table 4 Temperature Factor for All Microcircuits-πT

     

    		 TTL,
    ASTTL,CML,
    HTTL,FTTL,
    DTL,ECL,
    ALSTTL    		 BiCMOS,
    LSTTL    		 III,
    I3L,
    ISL    		 Digital MOS,
    VHSIC CMOS    		 Linear
    (Bipolar & MOS)    		 Memories
    (Bipolar & MOS), MNOS    		 GaAs MMIC GaAs Digital
    Ea(eV) →
    Tj(°C)    		 0.4 0.5 0.6 0.35 0.65 0.6 1.5 1.4
    25 0.10 0.10 0.10 0.10 0.10 0.10 3.2−9 1.0−8
    30 0.13 0.14 0.15 0.13 0.15 0.15 8.4−9 2.5−8
    35 0.17 0.19 0.21 0.16 0.23 0.21 2.1−8 5.9−8
    40 0.21 0.25 0.31 0.19 0.34 0.31 5.2−8 1.4−7
    45 0.27 0.34 0.43 0.24 0.49 0.43 1.3−7 3.1−7
    50 0.33 0.45 0.61 0.29 0.71 0.61 2.9−7 6.8−7
    55 0.42 0.59 0.85 0.35 1.0 0.85 6.7−7 1.5−6
    60 0.51 0.77 1.2 0.42 1.4 1.2 1.5−6 3.1−6
    65 0.63 1.0 1.6 0.50 2.0 1.6 3.2−6 6.4−6
    70 0.77 1.3 2.1 0.60 2.8 2.1 6.8−6 1.3−5
    75 0.94 1.6 2.9 0.71 3.8 2.9 1.4−5 2.5−5
    80 1.1 2.1 3.8 0.84 5.2 3.8 2.9−5 4.9−5
    85 1.4 2.6 5.0 0.98 7.0 5.0 5.7−5 9.4−5
    90 1.6 3.3 6.6 1.1 9.3 6.6 1.1−4 1.7−4
    95 1.9 4.1 8.5 1.3 12 8.5 2.1−4 3.2−4
    100 2.3 5.0 11 1.5 16 11 4.0−4 5.8−4
    105 2.7 6.2 14 1.8 21 14 7.5−4 1.0−3
    110 3.2 7.5 18 2.1 28 18 1.4−3 1.8−3
    115 3.7 9.2 23 2.4 35 23 2.4−3 3.1−3
    120 4.3 11 28 2.7 45 28 4.3−3 5.3−3
    125 5 13 35 3.1 58 35 7.5−3 9.0−3
    130 5.8 16 44 3.5 73 44 1.3−2 1.5−2
    135 6.7 19 54 3.9 92 54 2.2−2 2.4−2
    140 7.7 23 67 4.4 120 67 3.7−2 3.9−2
    145 8.8 27 82 5.0 140 82 6.1−2 6.3−2
    150 10 32 100 5.6 180 100 1.0−1 1.0−1
    155 11 37 120 6.3 220 120 1.6−1 1.6−1
    160 13 43 150 7.0 270 150 2.6−1 2.4−1
    165 15 50 180 7.8 330 180 4.1−1 3.7−1
    170 16 59 210 8.7 400 210 6.4−1 5.7−1
    175 18 68 250 9.6 480 250 9.9−1 8.5−1

    These are [the equations for the temperature factor].

    Ea: Effective Activation Energy (eV) (Shown Above)
    Tj: Worse Case Junction Temperature (Silicon Devices) or Average Active Device Channel Temperature (GaAs Devices).
    Note:
    Tj = Tc + P·θjc, Tc = Case Temperature (°C), P = Device Power Dissipation (W),
    θjc = Junction to Case Thermal Resistance (°C/W)
  3. C2: Package Failure Rate
    Table 5 Package Failure Rate for all Microcircuits-C2
    Package Type
    Number of Functional Pins, Np Hermetic: DIPS w/Solder or Weld Seal, Pin Grid Array (PGA)1, SMT (Leaded and Nonleaded) DIPs with Glass Seal2 Flatpacks with Axial Leads on
    50 Mil Centers3    		 Cans4 Nonhermetic: DIPs, PGA, SMT (Leaded and Nonleaded)5
    3 0.00092 0.00047 0.00022 0.00027 0.0012
    4 0.0013 0.00073 0.00037 0.00049 0.0016
    6 0.0019 0.0013 0.00078 0.0011 0.0025
    8 0.0026 0.0021 0.0013 0.0020 0.0034
    10 0.0034 0.0029 0.0020 0.0031 0.0043
    12 0.0041 0.0038 0.0028 0.0044 0.0053
    14 0.0048 0.0048 0.0037 0.0060 0.0062
    16 0.0056 0.0059 0.0047 0.0079 0.0072
    18 0.0064 0.0071 0.0058 – 0.0082
    22 0.0079 0.0096 0.0083 – 0.010
    24 0.0087 0.011 0.0098 – 0.011
    28 0.010 0.014 – – 0.013
    36 0.013 0.020 – – 0.017
    40 0.015 0.024 – – 0.019
    64 0.025 0.048 – – 0.032
    80 0.032 – – – 0.041
    128 0.053 – – – 0.068
    180 0.076 – – – 0.098
    224 0.097 – – – 0.12
    1. C2 = 2.8 × 10-4 (Np) 1.08    2. C2 = 9.0 × 10-5 (Np) 1.51
    3. C2 = 3.0 × 10-5 (Np) 1.82    4. C2 = 3.0 × 10-5 (Np) 2.01
    5. C2 = 3.6 × 10-4 (Np) 1.08
    Notes:
    1. SMT: Surface Mount Technology
    2. DIP: Dual In-Line Package
    3. If DIP Seal type is unknown, assume glass
    4. The package failure rate (C2) accounts for failures associated only with the package itself. Failures associated with mounting the package to a circuit board are accounted for in Section16, Interconnection Assemblies.
  4. πE: Environmental Factor
    Table 6 πE Environmental Factor
    Environment πE
    Ground, Benign
    Ground, Fixed
    Ground, Mobile    		 GB
    GF
    GM    		 0.50
    2.0
    4.0
    Naval, Sheltered
    Naval, Unsheltered    		 NS
    NU    		 4.0
    6.0
    Airborne, Inhabited, Cargo
    Airborne, Inhabited, Fighter
    Airborne, Uninhabited, Cargo
    Airborne, Uninhabited, Fighter
    Airborne, Rotary, Winged    		 AIC
    AIF
    AUC
    AUF
    ARW    		 4.0
    5.0
    5.0
    8.0
    8.0
    Space, Flight
    Missile, Flight
    Missile, Launch
    Cannon, Launch    		 SF
    MF
    ML
    CL    		 0.50
    5.0
    12
    220
  5. πQ: Quality Factor
    Table 7 Quality Factors-πQ
    Description πQ
    Class S Categories:
    1. Procured in full accordance with MIL-M-38510, Class S requirements.
    2. Procured in full accordance with MIL-I-38535 and Appendix B thereto (Class U).
    3. Hybrids: Procured to Class S requirements (Quality Level K) of MIL-H-38534.
    		 0.25
    Class B Categories:
    1. Procured in full accordance with MIL-M-38510, Class B requirements.
    2. Procured in full accordance with MIL-I-38535, (Class Q).
    3. Hybrids: Procured to Class B requirements (Quality Level H) of MIL-H-38534.
    		 1.0
    Class B-1 Category:
    Fully compliant with all requirements of paragraph 1.2.1 of MIL-STD-883 and procured to a MIL drawing, DESC drawing or other government approved documentation. (Does not include hybrids). For hybrids use custom screening section below.    		 2.0
    Table 8 Quality Factors (cont'd): πQ Calculation for Custom Screening Programs
    Group MIL-STD-883 Screen/Test (Note 3) Point Valuation
    1* TM1010 (Temperature Cycle, Cond B Minimum) and TM 2001 (Constant Acceleration, Cond B Minimum) and TM 5004 (or 5008 for Hybrids) (Final Electricals @ Temp Extremes) and TM 1014 (Seal Test, Cond A, B, or C) and TM 2009 (External Visual) 50
    2* TM 1010 (Temperature Cycle, Cond B Minimum) or TM 2001 (Constant Acceleration, Cond B Minimum)TM 5004 (or 5008 for Hybrids) (Final Electricals @ Temp Extremes) and TM 1014 (Seal Test, Cond A, B, or C) and TM 2009 (External Visual) 37
    3 Pre-Bum in ElectricalsTM 1015 (Burn-in B-Level/S-Level) and TM 5004 (or 5008 for Hybrids) (Post Bum-in Electricals @ Temp Extremes) 30 (B Level)36 (S Level)
    4* TM2020 Pind (Particle Impact Noise Detection) 11
    5 TM5004 (or 5008 for Hybrids) (Final Electricals @ Temperature Extremes) 11 (Note 1)
    6 TM2010/17 (Internal Visual) 7
    7* TM1014 (Seal Test, Cond A, B, or C) 7 (Note 2)
    8 TM2012 (Radiography) 7
    9 TM2009 (External Visual) 7 (Note 2)
    10 TM5007/5013 (GaAs) (Water Acceptance) 1
    11 TM2023 (Non-Destructive Bond Pull) 1

    This is [the equation for the quality factor].

    *Notes: appropriate for plastic parts.

    Notes:

    1. Point valuation only assigned if used independent of Groups 1, 2 or 3.
    2. Point valuation only assigned if used independent of Groups 1 or 2.
    3. Sequencing of tests within groups 1, 2 and 3 must be followed.
    4. TM refers to the MIL-STD-883 Test Method.
    5. Nonhermetic parts should be used only in controlled environments
      (i.e., GB and other temperature/humidity controlled environments).

    Examples:

    1. Mfg. performs Group 1 test and Class B bum-in:
      This is [the equation for the quality factor].

    2. Mfg. performs internal visual test, seal test and final electrical test:
      This is [the equation for the quality factor].
    Other Commercial or Unknown Screening Levels πQ = 10
  6. πL: Learning factor
    Table 9 Learning Factor πL
    Years in Production, Y πL
    ≤ 0.1 2.0
    0.5 1.8
    1.0 1.5
    1.5 1.2
    ≥ 2.0 1.0
    πL = 0.01exp (5.35 - 0.35Y)
    Y = Years generic device type has been in production
Links
Failure Rate Estimation Methods

On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Top of this page