Toshiba Corporation Semiconductor & Storage Products Company
HOME > Products > Reliability Information > Semiconductor Device Reliability > Semiconductor Device Reliability

On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Factors Affecting Reliability

[As of April, 2011]

Reliability Factor Analysis Techniques

In general, the analysis of reliability factors during product development and design and process design is very effective for improving reliability.
The main reliability factor analysis methods are:

  1. Design Review (DR)
  2. Fault Tree Analysis (FTA)
  3. Failure Mode and Effects Analysis (FMEA)
  4. Taguchi method

DR, in the case of semiconductor devices, refers to checking for any inconsistencies in the design of such items as shown in "Main Design Factors Affecting Reliability" and correcting any problems so as to yield a more complete product. Normally, a design standard is defined to simplify this process and incorporate corrections in advance. Design thus proceeds in accordance with the standard and is checked against the standard in the DR. If there are any deviations, tests are conducted to confirm compliance to the standard, corrections are incorporated in the design and the standard is updated as necessary.
FTA (Fault Tree Analysis) is used to analyze factors contributing to device failure, such as circuit configuration, pattern design, manufacturing process, package design and method of use.
FMEA (Failure Mode and Effects Analysis) is an analytical method used to confirm that corrective measures have been established for all possible failures in relation to aspects such as design, the manufacturing process and method of use.
The analysis divides aspects such as design, manufacturing process, packaging and methods of use into well-defined detailed smaller functional items. The possible failure modes for each item are then cataloged, and the effect of the failure on the product as well as failure causes are investigated. These items are then weighted so that countermeasure priorities can be defined and established.
Table 1 shows an example of the FMEA method for a resin-package MOS LSI manufacturing process. Using a scale of 1 to 10, the “R.P.N.” (Risk Priority Numbers)section of the table rates failure information in terms of occurrence , severity (on the product, equipment or system) and detection. “R.P.N.” is calculated by multiplying these three rated values together. The larger this value, the more serious the failure.
The last column in the table shows the processing and countermeasures for each item.
The Taguchi method is an effective method for minimizing variance to create a robust design. While conventional basic designs required a certain constant identified experimentally and theoretically for incorporating target outputs and characteristics, quality engineering parameter design introduces an S/N ratio (average value to variance ratio) as a measure of stability with respect to variance. A robust design is developed by creating a design that incorporates a standard with a high S/N ratio.
Table 2 shows an example of Taguchi method factors and an S/N ratio cause and effect diagram for mold resin package conditions in the resin-package MOS LSI manufacturing process. The table shows the results of testing based on “smaller-is-better” characteristics, using the L18 orthogonal array table.


Table 1 Manufacturing Process FMEA Example (Resin Molding)
Process Name (Process Function) Potential Failure Mode Potential Effect of Failure Potential Cause of Failure Failure Index Countermeasures
Occurrence Severity Detection R.P.N.
(1-10)
Al metallization
Improper thickness,
Al wiring flaws,
disconnection
Electromigration, open circuit Operator error, dirt, foreign particle adhesion, poor adjustment of equipment 2 9 2 36 Improvement and adjustment of work procedures, dust control in clean room, SEM inspection in process
(1-11)
Passivation
Lack of passivation film,
improper film thickness
Increased leakage current,
operation failure
Adherence of dirt and foreign particles, operator error 2 2 4 16 Dust control in clean room, improvement and adjustment of work procedures
(1-12)
Visual inspection
Scratch,
die crack,
contamination, blem,
residual photoresist
Open circuit, increased junction leakage current Mishandling of wafer, erroneous wafer cleaning 2 2 2 8 Improvement and adjustment of work procedures
2. Assembly process  
(2-1)
Die selection
Die crack Increased junction leakage current, operation failure Improper adjustment of equipment, operator error 1 3 2 6 Equipment control operator corrective action, improvement and adjustment of work procedures
(2-2)
Die bonding
Die crack, die floating Open, increased junction block leakage current, operation failure Operator error, temperature decrease 1 9 2 18 Equipment control operator corrective action, improvement and adjustment of work procedures, visual inspection
(2-3)
Wire bonding
Wire open, wire short, improper bonding position Open, short Improper bonding strength, operator error, poor adjustment of equipment, abnormal loop shape 2 10 1 20 Equipment control operator corrective action, improvement and adjustment of work procedures, visual inspection
(2-4)
Resin molding
Wire open, wire short, package crack, corrosion Open, short, defective appearance Poor adjustment of equipment, insufficient curing 2 10 2 40 Equipment control operator corrective action, improvement and adjustment of work procedures, visual inspection
(2-5)
Lead finishing (plating)
Improper plating thickness, dirt Poor soldering, improper contact Operator error, poor adjustment of equipment, insufficient cleaning 1 2 3 6 Improvement and adjustment of work procedures, equipment control operator corrective action
(2-6)
Lead forming
Abnormal shape, lead damage Improper printed circuit board insertion,
operation failure
Operator error, poor adjustment of equipment 1 2 1 2 Adjustment of work procedures, equipment control operator corrective action
(2-7)
Marking
Marking error, illegible marking Breakage during use Operator error, insufficient curing 1 1 1 1 Improvement and adjustment of work procedures

Table 2 Taguchi Method Example (Factors)
  Factor Unit Parameters
Standard 1 Standard 2 Standard 3
A Mold resin (mold name) - A1 A2 -
B Resin preheating time s B1 B2 B3
C Mold impregnation pressure Pa C1 C2 C3
D Metal mold clamp pressure t D1 D2 D3
E Metal mold temperature °C E1 E2 E3
F Time from molding to bonding H F1 F2 F3
G Mold ambient temperature return time H G1 G2 G3
H Mold service period H H1 H2 H3

This is [Figure 1 Taguchi Method Example (S/N Ratio Cause and Effect Diagram)].

Figure 1 Taguchi Method Example (S/N Ratio Cause and Effect Diagram)

On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Top of this page