On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Failure Analysis Procedure for General Semiconductor Products

[As of April, 2011]

When performing failure analysis, it recommends taking a systematic approach. An example is shown in Figure 1.

This is [Figure 1 Example of Failure Analysis Procedure].

Figure 1 Example of Failure Analysis Procedure

To obtain the data required for determining the failure mechanism, analysis should follow the flow shown.
Refer also to the failure analysis procedure defined in MIL-STD-883, Method 5003.
As soon as a failure sample is obtained, its history is investigated. Any related information, including manufacturing lot information (manufacturing date and storage period), failure information (whether the failure is total or intermittent, correlation to lot, failure rate), operating conditions (circuit conditions, thermal stress, mechanical stress) and environmental conditions (temperature, humidity, location, atmosphere), should be collected to aid in failure mechanism identification and simulation testing. Advance preparation of good samples for comparison with faulty devices is also an effective means of failure cause identification.
During the visual inspection, the exterior of the package is examined visually or with a stereo or metallurgical microscope in detail. Various failures can be identified in this way, allowing you to check abnormalities such as package cracks, migration between leads, rust or mechanical damage on leads. Surface elemental analysis is conducted as needed as part of the solid surface analysis described above in order to identify the failure cause.
Electrical characteristics are measured using a curve tracer, oscilloscope and testers, and the data is recorded. The quickest way to obtain failure mode data is by measuring the characteristics between terminals using a curve tracer. The failure mode is classified and the failure mechanism is analyzed based on a summary of failure investigation results, visual inspection results, electrical characteristics measurement results and past case examples and statistical data. Failure modes are broadly divided into three classifications: opens, shorts and degradation. Subsequent testing and analytical methods are determined based on this failure mode classification and failure mechanism estimation.
Before the device is de-encapsulated, baking, retesting, vibration testing, etc., are performed as needed to determine the failure mechanism. Also, an internal inspection by X-ray fluoroscopy is carried out prior to de-encapsulation to check wires and leads for opens and shorts.
The de-encapsulation method used to open the package is selected according to the presumed failure mechanism so as to enable semiconductor chip observation and analysis. If the de-encapsulation method is inappropriate, the necessary data may not be collectable, resulting in the failure cause to be left as unknown. Therefore, special precautions must be taken during package de-encapsulation.
De-encapsulation methods include: [1] dissolving using chemicals, [2] mechanical removal, and [3] incineration using a plasma reactor.
For ceramic and metal packages, mechanical de-encapsulation is easily achieved since no special equipment or tools are required.
The de-encapsulated sample is preferably analyzed immediately. However, if this is not possible, measures such as storing the device in a desiccator need to be considered to prevent contamination and mechanical damage after de-encapsulation.
The most convenient and quick way of observing internal conditions in detail is with a metallurgical microscope. A stereo microscope can be used to examine bonding and mounting conditions, and a scanning electron microscope can be used to make observations and take photographs at high magnification.
If the cause of failure cannot be assessed by microscope observation, elemental analysis and state analysis of the failure location are performed. Optimal methods and the equipment, such as EMPA, AES or SIMS, are selected according to purpose.
If the failure location cannot be assessed by internal state observation, other techniques such as wire electrical potential measurement using an EB tester, emission microscope analysis, the liquid crystal method, OBIC method or IR-OBIRCH method are considered effective means for failure location identification.
Furthermore, etching, cross-sectional cuts or specific cross-sectional cuts of detailed areas by FIB processing are used to examine the failure location and determine the failure mechanism.
Results obtained from the above analyses are fed back to the manufacturing process and stored in a data bank as failure case examples for the purpose of improving the device and enhancing reliability.