On July 1st, Toshiba Corporation's Semiconductor Company and Storage Products Company consolidated to form Semiconductor & Storage Products Company.This page describes reliability information of semiconductor products.

Identifying Failure Locations Using LSI

[As of April, 2011]

With recent trends in miniaturization, increasing multilayer wiring, increasing scales, faster speeds and increasing complexity, failure location identification has become increasingly difficult for LSIs. As a result, various LSI failure location identification techniques have been developed.
Figure 1 shows the general flow of failure location identification. The first step after failure occurrence is to reproduce the failure using some type of method. A study is then conducted to determine the optimum analytical method by the failure type. Once the method is selected, physical observations are made using analytical tools and instruments and the failure location is identified.

This is [Figure 1 Flow of Failure Location Identification].

Figure 1 Flow of Failure Location Identification

Figure 2 shows a detailed view of the failure analysis flow after failure reproduction. Although the tools and analytical instruments used differ according to failure type, in general the failure location is identified by roughly narrowing down the failure location (the analysis target) using software and other tools and physical observations, and then analyzing and conducting detailed physical observations of the circuits of the resultant area. Naturally, depending on the failure, the failure analysis flow will not necessarily proceed in this manner; the step of roughly identifying the failure location may be repeated or, conversely, may be used to identify the detailed failure location.

This is [Figure 2 Failure Analysis Flow].

Figure 2 Failure Analysis Flow

CAD Navigation System

When identifying a failure location, it is necessary to observe the circuit of the device you want to examine using an analytical instrument or identify a circuit location observed. To efficiently proceed with analysis over a short period of time, therefore, the target transistor or wire location to be observed or, conversely, the circuit area of the location that was observed must be promptly identified at the time of analysis. Yet, specifying the desired physical circuit location within a device is extremely difficult without use of design information (circuit and layout data) due to the increased scale and integration of devices in recent years. In cases such as this, the CAD navigation system is applied. This system allows you to link the device's physical coordinates on an analytical instrument with design information to simply trace the circuit without knowledge of layout design.
Figure 3 shows a display example of the CAD navigation system. In this figure, a) shows the observation screen for the emission microscope (EMS), b) the mask layout, and c) the circuit net list (equivalent to a circuit diagram that indicates the electrical connection relationship using text). The CAD navigation system enables observation screen and mask layout display interactive synchronization. Furthermore, the CAD navigation system also enables interactive synchronization of the mask layout and net list, indicating the corresponding wire and signal name by highlighting them in white, as shown in the figure.
By utilizing the CAD navigation system in this manner, the user can promptly identify the wiring location and chip location of the signal s/he wants to observe or, conversely, the layout location and circuit area of the location observed using an analytical instrument, thereby increasing analysis efficiency.
In addition, while this example shows the EMS observation screen, other analytical instruments can be used in the same manner.

This is [Figure 3 CAD Navigation System Display Examples].

Figure 3 CAD Navigation System Display Examples

Diagnostic Tool

To identify a failure location, a failure analysis instrument is required. This instrument allows you to conduct detailed investigations that will identify, for example, the location of a faulty transistor when a transistor fails. However, today's devices contain hundreds of millions of transistors. To identify the defective location by examining each transistor one by one is unrealistic. Since failure analysis instruments are more geared toward detailed analyses, it is important to first accurately narrow down the area to be observed so as to abbreviate the failure analysis TAT.
The diagnostic tool is used for this purpose. The diagnostic tool basically uses design information (circuit and mask layout information), test patterns and test results to logically narrow down possible locations of failure.
While many diagnostic methods have been proposed and developed into tools, the diagnostic method explained herein is the most basic method: one that employs a fault dictionary.

Methods Based on a Fault Dictionary

A simple explanation of a fault dictionary is provided below.
When testing a semiconductor device, a test pattern is used. This test pattern contains device input signals and expected output values. A diagnostic tool compares the expected value with the value actually output by the device, assessing the device as good or faulty based on whether or not the values are the same.
When the above-described test pattern is introduced into the device, it is possible to examine by logic simulation whether or not the output value is faulty based on failure scenarios for the signals within the circuit. A fault dictionary is developed for devices that involve a large number of signal failure scenarios that are known to result in faulty values. This dictionary summarizes when each faulty output value will occur for each presumed failure location. Figure 4 shows an example of a fault dictionary.
Figure 5 shows the method for extracting potential failures using the fault dictionary. For example, when a test pattern is introduced into a device, fail time information is obtained as a part of the test result. The fault dictionary is then used to examine signal failure scenarios for failures detectable at a fail time matching the fail time in the test result. In this example, the fail times of signals IN2 and IN3 are the same as that of the test result. These two signals are therefore extracted as possible failure locations.
While the example shown here is an extremely simple example, various techniques are incorporated in the diagnostic tool to further improve the accuracy of identifying possible failure locations. At present, however, diagnostic tools do not necessarily provide the answers for all failures that occur within a device, and cannot necessarily be used alone to identify failure locations. The diagnostic tool, however, can be used to narrow down the locations that should be examined using analytical instruments as described above, and is therefore extremely important in failure analysis.

This is [Figure 4 Fault Dictionary Example].

Figure 4 Fault Dictionary Example

This is [Figure 5 Example of Extraction of Possible Failure Locations Using Fault Dictionar].

Figure 5 Example of Extraction of Possible Failure Locations Using Fault Dictionary