Are there any rules on input with slow rising edge and/or trailing edge?

The rising edge and trailing edge time of input signal of the general-purpose CMOS logic are defined in recommended operating conditions.

The maximum value of the rising edge and trailing edge of the input signal that does not cause malfunction due to output oscillation are indicated.

If a signal with slow rising edge or trailing edge is applied, the spike current that is generated at switching fluctuates potentials of V_CC and GND lines, which may result in output oscillation or malfunction. Input of the gate or buffer may cause malfunction or oscillation, so attention should be paid to the control signals such as clocks.

Use Schmitt trigger ICs as a measure.

List of input rising and trailing time in recommended operating conditions
V_CC	series
	High speed	Advance	5V logic 3.3V low speed	low voltage low speed	low voltage middle speed	low voltage high speed
	TC74HC	TC74AC	TC74VHC	TC74LVX	TC74LCX	TC74VCX
5V	500ns	20ns/V	20ns/V	-	-	-
3.3V	-	100ns/V	100ns/V	100ns/V	10ns/V	10ns/V