Display Bridge/Hub
Toshiba's Display Bridge/Hub has various display interfaces to facilitate design of feature-rich mobile equipment realizing superb picture quality.
Examples of Display Bridge Configurations
MDDI to DSI-Display Bridge / TC358760/61XBG
Features
- Support MDDI 1.2 Direct refresh (60 fps) up to FWVGA
- LCD-I/F: MIPI® DSI 3lane
- Multiple display bridges:
MDDI->DSI/DPI/DBI, DPI/DBI->DSI - Resolution: Up to qHD, WSVGA, XGA (DPI-to-DSI mode)
- Host interfaces: MDDI 1.2 Type 1, DPI 24-bit , DBI-B 16-/18-bit
- LCD interfaces: DSI, DPI, DBI
General Specifications
| Supply voltages | 1.2 V (Core), 1.2 V & 1.8 V (MDDI I/O), 1.8-3.3 V (I/O) |
|---|---|
| Package dimensions | TC358760XBG : 3.5mm × 3.5mm (49 pins) TC358761XBG : 4.5mm × 4.5mm (72 pins) |
| Status / Availability | TC358760XBG : Mass Production TC358761XBG : ES Available |
DPI/DBI to DSI-Display Bridge / TC358763XBG
Features
- LCD-I/F: MIPI® DSI 3lane
- Multiple display bridges:
(DPI/DBI->DSI) - Resolution: Up to qHD, WSVGA, XGA (DPI-to-DSI mode)
General Specifications
- Host I/F:DPI 24bit/DBI-B 16/18bit
- LCD I/F:DSI
| Supply voltages | 1.2 V (Core), 1.2 V (MIPI I/O), 1.8-3.3 V (I/O) |
|---|---|
| Package dimensions | TC358763XBG : 4.5mm × 4.5mm (72 pins) |
| Status / Availability | Mass Production |
MIPI® Display Bridge / TC358762XBG
Features
- Host interface: MIPI® DSI
- Parallel display outputs: MIPI® DBI Type B, MIPI® DPI
- SPI, MIPI® DBI Type C and GPIOs for traditional peripheral interfaces, and I2C interface for internal register access
- qHD @70 fps (MIPI® DPI), FWVGA @60 fps (MIPI® DBI Type B)
- The source of the internal system clock is selectable from the DSI Clock or a clock derived by multiplying an external clock with on-chip PLL..
General Specifications
| Supply voltages | 1.2 V (Core), 1.2 V (MIPI® I/O), 1.8-3.3 V (I/O) |
|---|---|
| Package dimensions | 5.0mm × 5.0mm (64 pins) |
| Status / Availability | Mass Production |
MIPI® DSI to LVDS Bridge / TC358764XBG, TC358765XBG
Features
- Host interface: MIPI® DSI (DSI RX 4 lane)
- Single Link(TC358764XBG), Dual Link (TC358765XBG)
- I2C (master) and GPIO interfaces for peripheral device control and I2C (slave) interface for on-chip register programming
- TC358764XBG : Up to WXGA resolution (1366 × 768, 24 bpp)
TC358765XBG : Up to WUXGA resolution (1920 × 1200, 18 bpp; 1600 × 1200, 24 bpp)
General Specifications
| Supply voltages | 1.2 V (Core), 1.2 V (MIPI® I/O), 3.3 V (LVDS I/O), 1.8-3.3 V (I/O) |
|---|---|
| Package dimensions | TC358764XBG : 5.0mm × 5.0mm 0.65mm Ball pitch (49 pins) TC358765XBG : 6.0mm × 6.0mm 0.65mm Ball pitch (64 pins) |
| Status / Availability | Mass Production |
MIPI® DSI/DPI to Display Port Display Bridge / TC358766XBG
Features
- Host interface: MIPI®DSI (DSI RX 4 lane, 1 Gbps/lane), DPI (～154 MHz)
- Panel interface: VESA Display Port 1.1a (Single/Dual lane, 1.62 or 2.7 Gbps/lane)
- WUXGA: Up to (1920 × 1200, 24 bpp)
- HDCP 1.3 - I2C (slave) and SPI (slave) interfaces for internal register access
- Audio interface : I2S
General Specifications
| Supply voltages | 1.2 V (Core), 1.2 V & 1.8 V (Display Port), 1.2 V (MIPI® I/O) 1.8 V -3.3 V (I/O) |
|---|---|
| Package dimensions | 6.0 mm × 6.0 mm (120 pins) |
| Status / Availability | ES : 2012/Feb, Mass-production target: 2012/Q2 |
MIPI® DPI to MIPI® DSI Display Bridge / TC358768XBG
Features
- Host interface : MIPI® DPI (～154 MHz)
- Panel interface : MIPI® DSI (DSI RX 4 lane, 1 Gbps/lane)
- WUXGA: Up to (1920 × 1200, 24 bpp)
- I2C (slave) and SPI (slave) interfaces for internal register access
General Specifications
| Supply voltages | 1.2 V (Core), 1.8 V - 3.3 V (I/O), 1.2 V (MIPI® I/O) |
|---|---|
| Package dimensions | 4.5 mm × 4.5 mm (72 pins) |
| Status / Availability | Mass Production |