Automotive Display Controllers
Toshiba's automotive display controllers are designed to provide the capability to display instrument clusters, navigation systems and other in-vehicle applications. The controllers integrate a CPU, a graphics accelerator and a variety of interfaces on one single chip. All of which have the unified memory architecture (UMA).
- Display controllers available for low-end to high-end applications
- Integrated ARM Cortex™ and MIPS 64-bit CPU
- 24-bit color depth plus 8-bit alpha blending
- Powerful 2D/3D graphics accelerator
- Controllers with an embedded DRAM eliminate the need for external graphics memory.
- Distortion correction for fisheye-camera and head-up display
- Camera/video input with scaler
Roadmap
Toshiba will offer a full range of SoC and SiP products, from low end to high end, that incorporate the ARM Cortex™ core.
System Organization Example
TX4966 System Organization Example
TMPA970C20 System Organization Example
Automotive Display Controller : TX4966 Demo Video
This video clip introduces you fully-digital instrument panel system uses computer graphics replacing mechanical pointers and bulbs.
TMPA970C20 and TX4966 Display Capabilities
- 3D cover flow
-
- G1 3D Engine (TX4966), G2-Lite 3D Engine (TMPA970C20)
- Animation using OpenGL® ES 1.1 and 2.0
- Mirroring
- 2D cover flow
-
- High-quality motion pictures using Blitting Engine and Transformation Engines
- Antialiasing
System Features
Bus Architecture
Provides high-performance solutions thanks to the graphics accelerator, independent graphics bus and embedded DRAM.
Graphics Engine Overview
Lineup
| Feature | TX4966XBG-280 | TX4964FG-120 | TX4961XBG-240 |
|---|---|---|---|
| CPU core | 64-bit RISC TX49/L4 | 64-bit RISC TX49/L4 | 64-bit RISC TX49/H3 |
| Operating frequency | 280 MHz | 120 MHz | 240 MHz |
| Graphics accelerator | 2D/3D (Hardware) | 2D (Hardware) | 2D (Hardware) |
| 3D graphics | OpenGL® ES 1.1 | N/A | N/A |
| Camera/video inputs | 2 ch | 1 ch | 1 ch |
| Display outputs | 2 ch | 1 ch | 1 ch |
| A/D converters | N/A | N/A | 10-bit × 8-ch |
| CAN controllers | 4 ch | 2 ch | 3 ch |
| MediaLB® | Available | N/A | Available |
| External memory | SDRAM | N/A | DDR1 (512 MB max) |
| On-chip memory | SDRAM 8 MB | SDRAM 4 MB | N/A |
| Package | PBGA456 | LQFP176 | PBGA456 |
| Operating temperature range | -40℃ to 85℃ | -40℃ to 85℃ | -40℃ to 85℃ |
| Feature | TMPA970C20 [Under Development] |
TMPA972C20 [Under Development] |
|---|---|---|
| CPU core | ARM Cortex™-A9 Dual Core | ARM Cortex™-A9 Dual Core |
| Operating frequency | 336 MHz | 336 MHz |
| Graphics accelerator | 2D/3D (Hardware) | 2D/3D (Hardware) |
| 3D graphics | OpenGL® ES 2.0 | OpenGL® ES 2.0 |
| Camera/video inputs | 2 ch | Analog 4 ch Digital 1 ch |
| Display outputs | 2 ch | 1 ch |
| A/D converters | N/A | 10-bit × 15-ch |
| CAN controllers | 3 ch | 2 ch |
| MediaLB® | Available | N/A |
| External memory | DDR2 (512 MB max) | N/A |
| On-chip memory | 2 MB | 2 MB + DDR2 256 MB |
| Package | PBGA516 | PFBGA541 |
| Operating temperature range | -40℃ to 85℃ | TBD |
Product Introduction
Automotive Display Controller: TX4964FG-120
- 2D graphics accelerator
- On-chip eDRAM
- Reduced board assembly cost due to the QFP package
Features
- CPU: 64-bit TX49/L4 core; 120 MHz
- No floating-point unit
- 4-Mbyte eDRAM
- Graphics display controller with per-pixel alpha-blending
- 32-bit RGB alpha plane ×2
8-bit CLUT plane ×2
4-bit CLUT plane ×1
- 32-bit RGB alpha plane ×2
- 2D graphics accelerator
- Blit engine with alpha blending
Rotation engine
Transformation engine
- Blit engine with alpha blending
- Camera/video frame grabber
- RGB/YCbCr input interface
- Peripheral modules
Communication modules:- 2-channel full-CAN controller (TXCAN; two sets of 16 mailboxes)
- SPI (SEI) master/slave module with FIFOs
- SIO/UART with FIFOs
- 1-channel I2C module
- 2-channel I2S module
- 24-bit RTOS system timer
- Watchdog timer
- 3-channel 16-bit PWM timer
- 3-channel 16-bit timer
- Package: LQFP-176-2424-0.5
Automotive Display Controller: TX4966XBG-280
- 2D/3D graphics accelerator
- On-chip eDRAM
- Dual video inputs and outputs
Features
- CPU: 64-bit TX49/L4 core; 280 MHz
- 8-Mbyte eDRAM
- 2-channel graphics display controller (GDC) with per-pixel alpha-blending
- 32-bit RGB alpha plane ×5
- RGB/RSDS/APIX® output interface
- 2D/3D graphics accelerator
- 3D graphics core
- Blit engine with alpha blending
Rotation engine with alpha blending
Transformation engine with alpha blending
- 2-channel camera/video frame grabber
- RGB/YCbCr/APIX® input interface
- Peripheral modules
Communication modules:- 4-channel full-CAN controller (TXCAN; four sets of 32 mailboxes)
- 4-channel SPI (SEI) with FIFOs
- 2-channel SIO/UART with FIFOs
- 1-channel I2C module
- 2-channel I2S module
- MOST MediaLB® interface
- 24-bit RTOS system timer
- Watchdog timer
- 10-channel 16-bit PWM timer
- 8-channel 16-bit timer
- Package: PBGA456-2727-1.00
Automotive Display Controller: TMPA970C20 [Under Development]
- High performance CPUs (1680MIPS)
- Advanced 3D graphics accelerator
Features
- CPU: ARM Cortex™-A9 Dual Core
- Operating Frequency: 336 MHz
- DDR2 memory controller
- GDC with Alpha
- 4 Layers
- Dual display outputs (Digital RGB)
- 2D graphics accelerator
- Blit,Transformation,Rotation
- 3D graphics accelerator (OpenGL® ES 2.0)
- Camera / Video inputs
- RGB/ITU-R656
- Frame Grabber × 2
- Peripherals
- 3-channel Full-CAN (TXCAN, 4 × 32 mailboxes)
- 4-channel SPI
- 6-channel SIO/UART
- 2-channel I2C/3-channel I2S
- MOST MediaLB® interface
- 1-channel USB Host
- 8-channel 16-bit PWM timer
- Package:PBGA516-2727-1.00
![This is the block diagram of the TMPA970C20 Automotive Graphics Controller [Under Development].](/eng/product/assp/selection/automotive/infotain/display_controller/__icsFiles/artimage/2012/02/13/ec_asspcar15/AutDispCont12_e.gif "This is the block diagram of the TMPA970C20 Automotive Graphics Controller [Under Development].")
Automotive Display Controller: TMPA972C20 [Under Development]
- CPU: ARM Cortex™-A9 Dual Core
- Operating Frequency: 336 MHz
- 3D graphics accelerator (G2 Lite)
- API: OpenGL® ES 2.0
- 33 M polygons/sec, 264 M pixels/sec @132 MHz
- 2D graphics accelerator
- Rotation, Transformation
- LCD controller
- 4 Layers, 1280 x 720
- Embedded memory
- 256-Mbyte DDR2 SDRAM
with x32 bit data bus, Operating Frequency: 264 MHz - 2-Mbyte SRAM
- 256-Mbyte DDR2 SDRAM
- Video interface
- Input:4-channel Video SW (4 to 1 CVBS) with PAL/NTSC decoder
R656/R601
Video capture: 2-channel - Output: Digital RGB
- Input:4-channel Video SW (4 to 1 CVBS) with PAL/NTSC decoder
- Audio interface
- Input:I2S x1
Analog audio from MIC (mono) - Output:I2S x1
Analog audio : 3-channel (mono & stereo) - SRC: in: 8 k to 48 kHz, out: 44.1 k or 48 kHz
- Input:I2S x1
- 1-seg interface (T.B.D)
- Input: TS (CLK, DATA, EN)
- Peripherals
- USB 2.0 (Host)
- SD x2: SDHC support
- CAN x2: up to 1 Mbps, with Transceiver (1-channel)
- SPI x4, UART x6, I2C x2, PWM x6, GPIO x36 ‥ multiplexed
- Package:PFBGA541-2222-0.65AF
![This is the block diagram of the TMPA972C20 Automotive Graphics Controller [Under Development].](/eng/product/assp/selection/automotive/infotain/display_controller/__icsFiles/artimage/2012/03/07/ec_asspcar15/AutDispCont13_e.gif "This is the block diagram of the TMPA972C20 Automotive Graphics Controller [Under Development].")
* ARM, ARM Cortex and ARM Cortex-A9 MP Core are trademarks or registered trademarks of ARM Limited in the EU and other countries.
* APIX® is a trademark or registered trademark of Inova Semiconductors Inc.
* System and product names mentioned herein may be trademarks or registered trademarks of respective companies or organizations.