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Benefits of the Toshiba ASICs

By leveraging comprehensive ASIC expertise ranging from design to manufacture, Toshiba is working on the development of silicon processes, packages, design infrastructure and design methodologies. Toshiba exerts all these technologies to offer one-stop services covering system-on-chip (SoC) design, prototyping, testing and mass production. Our experienced project leaders provide customer support and development management throughout the entire project cycle. Rest assured, you can create competitive SoC-based products at a low cost in a short period of time. Toshiba has sufficient manufacturing capacity to ensure stable availability of your SoC

Comprehensive ASIC Capabilities from Design to Manufacture

Design, manufacturing, packaging and other technologies must be combined in an appropriate way to create advanced SoCs. Our development efforts encompass silicon processes, packages, design infrastructure and design methodologies. Toshiba exerts all these technologies to offer one-stop services covering system-on-chip (SoC) design, prototyping, testing and mass production. Toshiba brings you not only competitive SoCs at a low cost in a short period of time, but also sufficient manufacturing capacity and reliability.

State-of-the-art comprehensive SoC capabilities encompassing design, manufacturing, evaluation and analysis
  • Customer support and development management by Toshiba's experienced project leaders throughout the project cycle, from product planning to post-manufacturing analysis
  • Total performance budgeting and optimization across the chip, package and system (CPS) domains
  • Design-for-manufacturability (DFM) and design-for-testability (DFT) to improve yield and reliability

* DFM: Design for Manufacturing
* DFT: Design for Test

This figure shows the strengths of an IDM.

Various Design Interface Levels from ASIC to COT

Toshiba provides a number of customer interface levels. You can select your level of design participation to push your design to optimal performance and make the best use of your in-house capabilities.

This figure illustrates various design interface levels.

* COT: Customer Owned Tooling

High-Level Design Approaches

Not only is there a rapid increase in device complexity and performance, there is also a market demand for reducing power consumption at the same time. Consequently, the design process is becoming increasingly complicated, making architecture exploration, functional design and verification, and physical design more time-consuming. To meet today’s short time-to-market goal, design turnaround time must be short. To address this challenge, high-level design approaches are necessary, such as feasibility studies prior to actual design, accurate prototype design, a formalized design flow and quantification of design progress. Toshiba supports high-level design using silicon virtual prototyping (SVP) and chip-package-system (CPS) codesign.

Silicon virtual prototyping (SVP) provides accurate estimates of detailed physical implementation at the beginning of the design flow.

This figure provides an overview of Silicon Virtual Prototyping (SVP).

Chip-package-system (CPS) codesign extracts an accurate package model early in the design flow to enable signal and power integrity analysis.

This figure provides an overview of the Chip-Package-System (CPS) codesign technology.

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Quick Turnaround Time (TAT)

Toshiba supports quick turnaround from tapeout to the delivery of engineering samples helping to reduce system development time. The turnaround time varies depending on the process technologies, delivery forms (wafers, chips or packaged samples), quantities and so on. For details, please contact your local Toshiba sales representative.

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