Embedded DRAM (eDRAM) ASICs

The low-power and high-bandwidth characteristics of Toshiba's embedded DRAM make it ideal for a wide range of applications, including video/image processing devices such as graphics and display controllers; storage devices such as HDD controllers; and digital communication and networking devices.

Key Features of DRAM Cores

1. Much denser than SRAM
2. High performance with fast data transfer rates due to wide on-chip memory buses, compared to commodity DRAMs.
3. Low power
4. Built-in test circuitry and redundancy circuitry
5. Flexible core cells generated by a DRAM macro generator

Features of Toshiba's DRAM Cores

DRAM Cores for the TC320 Series

DRAM cores are available for the TC320C cell-based ICs. All primitive cells and I/O cells for the TC320C can be used without compromising their performance.

Specifications of DRAM Cores for the TC320C Cell-Based IC Series

Characteristics	LP
Random Access Cycle Time	32 ns
Latency	1, 2, 3
Max Clock Frequency (Page Mode)	250 MHz
Memory Capacity	4 to 32 Mb
Bit Width	64/128/256

DRAM Cores for the TC300 Series

DRAM cores are available for the TC300C cell-based ICs. All primitive cells and I/O cells for the TC300C can be used without compromising their performance.

Specifications of DRAM Cores for the TC300C Cell-Based IC Series

Characteristics	SD	SD (LP)*
Random Access Cycle Time	36 ns	40 ns
Latency	1, 2, 3	1, 2, 3
First Data Output Time	-	-
Max Clock Frequency (Page Mode)	222 MHz	200 MHz
Memory Capacity	4 to 32 Mb	4 to 32 Mb
Bit Width	64/128/256	64/128/256

DRAM Cores for the TC280 Series

The TC280C cell-based ASIC series offers a variety of embedded DRAM cores. Designers can use the same primitive and I/O cells as well as any IP cores available for the TC280C pure logic process without compromising logic performance. The DRAM cores for the TC280 series have the following two types:

Standard Synchronous DRAM (SD) Macros

The standard SD macros are available in a variety of capacities and operate over a wide range of clock frequencies.
The SD macros are suitable for applications requiring fast page-mode accesses.

Fast-Access DRAM Macros with Faster Random Access and Data Output

Two types of the fast-access (FA) DRAM macros offer significant advantages over the SD macros in random-access cycle time or data output times.

1. FA-RC macros have fast random-access cycle times.
   The FA-RC macros are ideal for applications requiring fast random accesses.
2. FA-AC macros have fast first data output times.
   The FA-AC macros achieve the fast page-mode access.

Specifications of DRAM Cores for the TC280C Cell-Based IC Series

Characteristics	SD	FA-RC	FA-AC
Random Access Cycle Time	40 ns	10 ns	12 ns
Latency	1, 2, 3	1, 2	2
First Data Output Time	-	14 ns	10 ns
Max Clock Frequency (Page Mode)	200 MHz	-	200 MHz
Memory Capacity	4 to 32 Mbits	2 to 9 Mbits	2 to 9 Mbits
Bit Width	64/128/256	128/144/256/288	128/144/256/288

DRAM Cores for the TC260 Series

The DRAM cores for the TC260 series having 0.14-μm gate length is fabricated using the 0.14-μm process technology. SD and FA cores are available.

Specifications of DRAM Cores for the TC260 Series

Characteristics	SD	FA
Random Access Cycle Time	48 ns	15 ns	12 ns	15 ns
Latency	1, 2, 3	1	2	2
Max Clock Frequency (Page Mode)	181 MHz	-	-	200 MHz
Memory Capacity	2 to 32 Mbits	2 Mbits, 4 Mbits

Contacts

If you have any queries, click one of these links:

• Technical queries
  • Contact Us
• Queries about purchasing, sampling and IC reliability
  • Overseas Sales

• Products
  • ASICs
    • Product Introduction
      • CMOS ASIC Types
• Applications
• Company Profile
• News and Event
• Support
• Environmental Activities

• Terms of Use
• Site Map