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SCS (Stacked Chip SoC)

Features of Stacked Chip SoCs (SCS)

Stacked Chip SoC (SCS) is a kind of system-in-package (SiP) that uses chip-on-chip (CoC) technology to interconnect the stacked chips with microbumps. For example, SCS can be used to connect an ASIC chip with a DRAM chip. This approach provides both a data transfer rate equivalent to an embedded-DRAM ASIC and a large memory capacity that is difficult to achieve with an embedded-DRAM ASIC. SCS is ideally suited for applications that require high-bandwidth data transfers.

This figure provides an overview of Stacked Chip SoCs (SCS).

Compared to flip-chip bumps on FC-BGA substrates, microbumps provide a smaller bump size and a tighter pitch. They offer very low parasitic capacitance, making it possible to use buffers with low drive strengths, as on-chip buffers for chip-to-chip data transfers. Additionally, microbumps have low inductance and thus help to reduce EMI noise.

This is a photo of microbumps.

SCS supports ultra-high-pin-count CoC connection. Even if each memory I/O is relatively slow, a high data transfer rate can be achieved, thanks to the wide bandwidth. This helps to reduce the SCS’ overall power dissipation. As is the case with the conventional system-in-package (SiP), significant board space savings are possible with the use of SCS.

This figure provides an overview of Stacked Chip SoCs (SCS).

SCS Roadmap


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