ASICs / Structured Arrays
Chip-Package-System (CPS) Codesign Technology
Toshiba has developed a chip-package-system (CPS) codesign/coverification platform. Its concept is collaborative development of the chip, package and PCB system board by creating an accurate virtual package model before the designing of a package substrate begins based on the final specification of the integrated chip-package design. Chip-package-system codesign allows optimal cost/performance trade-offs, reduces IC and system development times and improves verification accuracy prior to actual system hardware prototyping.
Process geometries continue to shrink, enabling IC designers to implement more complex and higher-performance designs. Today, IC designers are dealing with increasingly complex designs and tightening design cycles. On the PCB system front, an increase in the amount of data to be transmitted between ICs is pushing up system data rates; it is creating signal and power integrity (SI/PI) challenges across the chip, package and PCB design domains. Signal and power integrity issues are becoming increasingly important across the domains to assure design quality. However, the chip, package and PCB system designs have traditionally been a series of sequential and independent steps. To ensure a successful design, the traditional approach can lead to over-design, which in turn can create design difficulties and increase development times and costs. To address such problems, a new methodology is being required.
Concept of chip-package-system codesign/coverification technology
1. Early cost/performance trade-offs at the product planning stage
The CPS technology platform includes Toshiba’s proprietary chip planner, a quick virtual package design tool, and PI and SI analysis tools. These tools enable IC designers to perform quick signal and power integrity checks early in the design cycle when pin assignment and design information become available. Thus IC designers can select an appropriate package and reduce unnecessary power/ground pins, thereby cutting IC costs. They can also validate the die-pad allocations of their IC designs and the feasibility of the initial package specification. The suite of tools is designed with a seamless interface to eliminate manual work in the design chain and thus enables a very quick validation.
2. Benefits of chip-package-system codesign
The new codesign approach allows IC designers to create a detailed virtual package substrate while the designing of a chip prototype is still in progress. The virtual package substrate provides for an extraction of its power/ground model. It enables a chip’s IR-drop analysis in the presence of package effects, which has traditionally been done with packaging left as an afterthought. Additionally, simultaneous use of the chip’s, package’s and PCB’s power/ground models allows a power integrity analysis of the chip-package-system design.
From the package substrate model, you can extract an accurate SPICE model; by using a chip’s I/O model, its package’s SPICE model and a PCB model, you can perform signal integrity and timing verification on the chip-package-system design before a detailed chip design is completed. This makes it possible to achieve the best performance on the chip by reducing over-design. Also, a design feasibility study of the PCB board helps improve verification accuracy prior to system hardware prototyping.
3. Reduction in development times
The traditional approach to product development is a series of sequential and isolated steps for chip, package and PCB designs. In this approach, later steps must wait until earlier steps complete. The designing of a package can not begin until a chip design is finalized, and chip and PCB verification can not begin until a package design is available. If design goals are not met during the final chip or PCB verification, you may have to iterate over the entire design cycle, resulting in increased turnaround times.
On the other hand, the new codesign approach requires the designing of an accurate virtual package and an extraction of its model. As a prerequisite to creating an actual package design, a chip is co-designed with its package and PCB. Designers in these domains can achieve more parallel work and greater collaboration. Together, they can complete product development in a shorter time.
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