Low-Power Technology
Overview
As SoCs become increasingly large and complex, their power problems are becoming a limiting factor. To address these problems, Toshiba provides various low-power techniques, as listed in the table below. At the system level, you need to consider the active power a system consumes when it is running and the standby power it consumes in the standby state. At the transistor level, you need to reduce the dynamic power dissipated due to the switching of transistors and the leakage power dissipated as long as power is supplied to the SoC. Toshiba offers low-power solutions at both the system and transistor levels.
| Standby | Active | |
|---|---|---|
| Dynamic | - | Memory partitioning Datapath optimization Clock gating Low-power synthesis Low-power flip-flops On-chip power supply control fV (frequency/voltage) control Power-aware clock tree synthesis Substrate biasing |
| Leakage | Multi-Vth (threshold voltage) optimization Multi-L (gate length) optimization On-chip power supply shutdown Low-power flip-flops High-Vth SRAMs Data-retention flip-flops Leakage cut-off schemes for SRAMs |
Multi-Vth (threshold voltage) optimization Multi-L (gate length) optimization fV (frequency/voltage) control Low-power flip-flops High-Vth SRAMs Runtime power gating |
Low-Power Flip-Flops
Flip-flops constitute a large proportion of a chip’s overall power dissipation. To address this problem, Toshiba offers various flip-flops specifically designed for power reduction. The proper use of these flip-flops helps to reduce a circuit’s power dissipation.
- Conditional clocking flip-flops
- Data mapping flip-flops
- Adaptive coupling flip-flops
- Example: Data mapping flip-flops
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Data mapping flip-flops map their data inputs to a configuration that eliminates redundant internal transitions. Use of pulse-triggered logic not only reduces a flip-flop’s power dissipation but also speeds up its performance.
Power Supply Control Techniques
Switching power is proportional to the square of the supply voltage. Thus, you can greatly reduce switching power by controlling the supply voltage appropriately. Additionally, since the entire design continues to dissipate leakage power as long as the power supply is maintained, you can reduce leakage by powering down portions of a design when they are inactive. The following introduces two techniques of power supply control: multi-VDD design and power supply shutdown.
- Multi-VDD Design
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This technique divides a design into a number of voltage islands and associates them with different supply voltages according to their performance requirements. In the example shown at right, Block 1 is a voltage island with a lower voltage; it dissipates 30% less power per gate/MHz than the other blocks. Toshiba offers level shifters that need to be inserted between different voltage islands, and a power-aware design environment for multi-VDD designs.
- Power Supply Shutdown
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This technique inserts power switches specifically designed to cut off leakage current to certain circuit blocks. The power supply to each circuit block is controlled through on-chip power switches. In the example shown at right, Block 1 and Block 3 have power switches. The effect of using them depends on how often the associated blocks become totally inactive.
Toshiba also offers special flip-flops called data retention flip-flops, which retain data even when power is removed. Use of data retention flip-flops provides flexible trade-offs between power recovery times and leakage power reductions. You can combine power supply shutdown with multi-VDD design to reduce both switching and leakage power.
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