Physical Layout Techniques
Overview
Recently, we have come to grips with large and fast SoC designs with over 50 million gates. To leverage the advanced silicon technology, an enhanced EDA technology is also be required. As SoC designs become increasingly large and complex, the physical layout technology holds the key to not only shortening design time but also creating high-performance SoCs. To help create large, high-performance SoCs in a short period of time, Toshiba has developed integrated design environments called Orion DK and Apex DK built on the state-of-the-art Synopsys IC Compiler and Magma Talus Vortex. These Design Kits (DKs) are tightly coupled with sign-off environments, package CAD systems and automatic test equipment (ATE), making it possible to create optimal SoC designs.
Layout Features
- Creates large, high-performance SoCs in a short period of time
- Supports both feasibility and implementation phases
- Supports a low-power design flow
- Creates low-power and high-speed SoCs thanks to an advanced clock tree synthesis (CTS) technique
- Provides high-performance timing closure and signal integrity (SI) solutions to create reliable SoCs
- Supports Multi-Corner Multi-Mode (MCMM) optimization
- Offers DFM Prevention and Auto Fixing capabilities to ensure a reliable design cycle
Feasibility Phase
In the feasibility phase, an incomplete netlist is used to assess the prospects for design success. Toshiba offers an automatic floorplanner, which allows you to create a high-quality floorplan in one-fifth the time compared to using the conventional floorplanners. This makes it possible to quickly check chip sizing, ease or difficulty of SI-aware timing closure and power supply conditions before a final netlist becomes available. The new floorplanner helps to shorten overall design time and push your SoC to higher performance levels.
Implementation Phase
The feasibility phase is followed by the implementation phase in which you create a physical layout from a final netlist. Generally, large SoC designs are hierarchically broken into sub-blocks of manageable size that you can lay out individually. After all sub-blocks are laid out, they are assembled into a single chip. At the sub-block level, a state-of-the-art P&R tool is employed to perform place-and-route, as well as timing-, power-, SI- and DFM-aware optimizations. After layout, a design is transferred to a sign-off environment to perform SI-aware STA, check crosstalk noise and IR-drop, run litho simulation, and perform DRC, ERC and LVS.
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