Design Methodologies

Design Flows

Development Flow & Supported EDA tools: In keeping with its overriding commitment to customer support, Toshiba offers flexible support services to meet and exceed customer needs. You can choose the degree of your involvement in the sequence of ASIC development from a wide variety of levels such as initial specification development, RTL design/verification, logic design, physical layout and prototyping. Toshiba supports various electronic design automation (EDA) tools, so you can work with tools you feel comfortable with. Toshiba’s ASIC design environment materially shortens development time, reduces development costs and improves design productivity.

Low-Power Technology: At the system level, you need to consider the active power a system consumes when it is running and the standby power it consumes in the standby state. At the transistor level, you need to reduce the dynamic power dissipated due to the switching of transistors and the leakage power dissipated as long as power is supplied to the SoC. Toshiba offers low-power solutions at both the system and transistor levels.

DFM (Design For Manufacturing): With shrinking process technologies, design-for-manufacturing (DFM) is becoming of utmost importance. Toshiba uses a DFM flow as shown below in order to ensure maximum yield and quality. DFM optimization provides low-cost and fast-turnaround solutions for SoC design.

Statistical Variation-Aware Design: Toshiba offers a statistical STA (SSTA) environment in which timing analysis can statistically take variations into account. You can now use an STA tool for statistical timing analysis that has traditionally been left to SPICE Monte Carlo simulations. At the 40-nm node and below, variations among different portions of a chip are prominent, increasing the need for an STA technique capable of predicting them accurately.

Design-for-Test (DFT): High-quality tests are necessary to reduce the defect level, or the probability that defective chips are shipped. Toshiba supports various design-for-test (DFT) techniques such as memory BIST, compressed scan, on-chip clock control (OCC), low-power testing and JTAG boundary scan. Toshiba offers automatic DFT environments that can generate high-quality test patterns.

Physical Layout Techniques: Toshiba offers integrated design environments built on state-of-the-art P&R tools, which help to create high-performance, complex system-on-chip (SoC) designs in a short period of time. They are tightly coupled with sign-off environments, package CAD systems and automatic test equipment (ATE), facilitating the development of optimal SoCs.

Selecting a Package Considering Thermal Performance: You should consider thermal solutions at the system level when selecting a package for your SoC. Since an SoC package is an integral part of a system, you need to evaluate heat transfer paths from the SoC package. You should choose a package with a structure conducive to good heat transfer. Toshiba offers thermal simulation services, if necessary, to give you advice on packaging.

Package/Board Optimization Through Electrical Performance Analysis: While ASICs/SoCs are becoming faster, supply voltages are getting lower and lower. Consequently, ASIC/SoC packages have come to have a significant impact on the overall system performance. Additionally, for reliable system operation, a pc board should be designed with an optimal power delivery network (PDN). Toshiba extracts a package model during ASIC/SoC development, runs simulation and feeds back its result to package design. The package model is provided to you.

Chip-Package-System (CPS) Codesign Technology: Toshiba has developed a chip-package-system (CPS) codesign/coverification platform. Its concept is collaborative development of the chip, package and PCB system board by creating an accurate virtual package model before the designing of a package substrate begins based on the final specification of the integrated chip-package design. Chip-package-system codesign allows optimal cost/performance trade-offs, reduces IC and system development times and improves verification accuracy prior to actual system hardware prototyping.

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